The present invention relates to a semiconductor integrated circuit device, and more specifically to implementing, for example, a time keeping function on a semiconductor integrated circuit device such as a single-chip microcomputer.
In an electronic desk-top calculator comprised of a microcomputer and semiconductor integration circuits, an oscillation circuit using a quartz oscillator produces raw clock signals for operating the system. When such a data processing system is intermittently operated, the oscillation circuit is stopped. This causes the operations of the microprocessor and memory to temporarily stop, thus reducing the consumption of electrical power. To achieve this reduction, a hold function is provided to stop the system clock upon receipt of a control signal from an external unit or an instruction from the microprocessor.
In a semiconductor integrated circuit device such a microcomputer having a real time clock function, the raw clock signals cannot be stopped if the oscillation circuit is utilized for both time keeping and the system clocks. To overcome this limitation a microcomputer which uses a quartz oscillation circuit of 32.768 KHz for timekeeping and a cheaply constructed RC oscillation circuit or an oscillation circuit using a ceramic oscillator for the raw system clock (about 4 MHz) has been proposed. A microcomputer equipped with such two oscillation circuits has been described, for example, in "Hitachi 4-Bit 1-Chip Microcomputer System, MMCS 40 Series, LCD-III, User's Manual", third edition, No. 4, Hitachi, Ltd., June, 1984, pp. 4 and 24-25.
When the raw high frequency oscillation in the microcomputer is stopped during the holding state, the suspended oscillation circuit must be re-energized at least every second to maintain a real time system clock for the timekeeping function. The present inventors found that a relatively long stabilization waiting time before resuming oscillation results in unstable oscillation of the high frequency. This consumes large amounts of electrical power.
The present inventors also studied using a low frequency to form system clocks by switching the output of the oscillation circuit for timekeeping during the halting operation (subactive). In this case, the present inventors found that the basic clock frequencies for timekeeping and for the system clocks do not have an integer number ratio which would exits if the frequencies were 32 KHz and 4 MHz for example; i.e., the oscillation operations are not performed synchronously. When the two clocks are switched (active/subactive), this lack of synchronization causes extremely narrow pulses SP and undesirable wide pulses WP in the system clocks as shown in FIG. 6. This results in erroneous system operation when the clocks are switched.